1. Field of the Invention
The present invention relates to a lateral double diffused MOS field effect transistor using an SOI (Silicon On Insulator) substrate, a so-called SOI LDMOSFET (Lateral Double Diffused MOSFET).
2. Description of the Related Art
Conventionally, semiconductor relay has been known as a switching element which turns on and off a signal and power. The semiconductor relay includes in a package a light emitting element such as a light emitting diode, a light receiving element such as a photodiode, and a semiconductor switching element which is turned on and off by an output of the light receiving element. For the semiconductor switching element, a power MOSFET having no offset of an output signal to an input signal and having a high breakdown voltage is generally used.
A semiconductor switching element used for a semiconductor relay is desired to have a small capacitance between output terminals of a relay relevant to a high-frequency signal shielding performance at an off time. A main component which determines this capacitance between the output terminals becomes an output capacitance of the power MOSFET. Based on this background, in recent years, there has been proposed to use for a semiconductor switching element an LDMOSFET using an SOI substrate, a so-called SOI LDMOSFET, capable of reducing an output capacitance and reducing a size by integration than those of a conventional VDMOSFET (Vertical Double Diffused MOSFET) (see Japanese Patent Application Laid-open No. H11-186555).
A parasitic capacitance of the SOI LDMOSFET includes a gate-drain capacitance Cgd, a gate-source capacitance Cgs, a drain-source capacitance Cds, a drain-substrate capacitance Cdsub, and a source-substrate capacitance Cssub. An output capacitance Coss of the SOI LDMOSFET becomes a sum (Cgd+Cds+Cdsub) of the gate-drain capacitance Cgd, the drain-source capacitance Cds, and the drain-substrate capacitance Cdsub. However, according to the conventional SOI LDMOSFET, the drain-substrate capacitance Cdsub has a size that cannot be disregarded. Therefore, it is difficult to further reduce the output capacitance Coss.
The present invention has been achieved to solve the above problems, and an object of the invention is to provide a semiconductor device capable of reducing an output capacitance.